LRZ-Newsletter Nr. 05/2019 vom 07.05.2019
Unsere Themen:
-
Neuigkeiten
-
Termine, Kurse und Veranstaltungen
- Firewall: Einführungs- und Fortgeschrittenen-Kurs am LRZ
- Frühjahrstreffen des Arbeitskreises "Multimedia & Grafik" des ZKI
- PRACE Workshop: HPC code optimisation workshop
- Introduction to Intel FPGA Programming Models
- NEW PRACE Course: Deep Learning and GPU programming workshop @ LRZ
- NEW: Deep Learning and GPU programming using OpenACC @ HLRS Stuttgart
- Next HPC Courses at LRZ
-
Stellenangebote/Job Opportunities
- Stellenangebot: Fachinformatiker (m/w/d) für den IT- Service Desk
- Stellenangebot: Verwaltungsmitarbeiter/in (m/w/d) im Empfang
- Stellenangebot: Mitarbeiter/in (m/w/d) Netzmanagement
- Studentische Hilfskraft (m/w/d) - Automatisierung im Software Engineering
- Studentische Hilfskraft (m/w/d) für den Bereich Human Resources
- Studentische Hilfskraft (m/w/d) Web/JavaScript/TypeScript
- Studentische Hilfskräfte (m/w/d) am Service-Desk
- Initiativbewerbungen
-
Impressum, Abbestellen des Newsletters und Archiv
Neuigkeiten
Schwarzes Loch: Bild auch dank SuperMUC
Natürlich wollen auch wir zuerst den über zweihundert Wissenschaftlerinnen und Wissenschaftlern gratulieren, die daran mitgewirkt haben, das erste Bild eines schwarzen Lochs aufzunehmen, vor allem auch unseren Nachbarn bei der ESO nebenan auf dem Forschungscampus Garching!Forschungen wie diese sind ohne Höchstleistungsrechner nicht möglich. Und so hat auch SuperMUC am LRZ seinen Anteil daran, wie es in der Veröffentlichung heißt: "The simulations were performed in part on the SuperMUC cluster at the LRZ in Garching, on the LOEWE cluster in CSC in Frankfurt, and on the HazelHen cluster at the HLRS in Stuttgart."
Am LRZ abzugebende Geräte
Die folgenden Geräte werden an Interessenten aus dem Hochschulbereich oder aus anderen Behörden kostenlos abgegeben. Senden Sie bitte bei Interesse bis spätestens 21.05.2018 eine Nachricht an die E-Mail-Adresse: Althardware_AT_lrz.de. Wir werden dann mit Ihnen Kontakt aufnehmen.|
Anzahl |
Typ |
Modell |
Baujahr |
CPU |
RAM GB |
DISK GB |
Bemerkung |
|
2 |
Drucker |
Xerox Phaser 5500 DTM |
2006 |
|
|
||
|
1 |
Drucker |
Xerox Phaser 7400 |
2006 |
|
|
||
|
|
|
|
|
|
|
|
|
|
1 |
Desktop |
Dell Optiplex 760 |
2008 |
Core 2 Duo |
2 |
250 |
|
|
1 |
Desktop |
Dell Optiplex 780 |
2010 |
i5 |
4 |
keine |
|
|
4 |
Desktop |
Dell Optiplex 980 |
2010 |
i5 |
4 |
320 |
|
|
1 |
Desktop |
Dell Optiplex 980 |
2010 |
i5 |
4 |
keine |
|
|
3 |
Desktop |
Dell Optiplex 990 |
2011 |
i5 |
4 |
keine |
|
|
2 |
Desktop |
Dell Optiplex 990 |
2011 |
i5 |
4 |
320 |
|
|
4 |
Desktop |
Dell Optiplex 790 |
2012 |
i5 |
8 |
500 |
|
|
6 |
Desktop |
Dell Optiplex 7010 |
2013 |
i5 |
8 |
250 |
|
|
|
|
|
|
|
|
|
|
|
1 |
Monitor |
Hitachi 15“ |
1999 |
|
|
|
|
|
1 |
Monitor |
Dell 17“ |
2001 |
|
|
|
|
|
9 |
Monitor |
Dell 19“ |
2006 |
|
|
|
|
|
15 |
Monitor |
Dell 20“ |
2004 - 2008 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
Laptop |
Siemens Lifebook P7010 |
2005 |
Centrino |
2 |
keine |
|
|
2 |
Laptop |
Dell Latitude E6400 |
2008 |
Core 2 Duo |
4 |
160 |
|
|
1 |
Laptop |
Dell Latitude XT |
2008 |
Core 2 Duo |
3 |
64 |
|
|
1 |
Laptop |
Dell Latitude XT2 |
2009 |
Core 2 Duo |
3 |
120 |
|
|
4 |
Laptop |
Dell Latitude D630 |
2009 |
Core 2 Duo |
4 |
120 |
|
|
1 |
Laptop |
Dell Latitude E4200 |
2009 |
Centrino 2 |
3 |
120 |
|
|
1 |
Laptop |
Dell Latitude E4300 |
2009 |
Core 2 Duo |
4 |
120 |
|
|
5 |
Laptop |
Dell Latitude E64x0 |
2011 |
i5 |
8 |
256 |
|
|
1 |
Laptop |
Dell Latitude M11 |
2011 |
i7 |
8 |
128 |
|
|
2 |
Laptop |
Dell Latitude E5420 |
2012 |
i5 |
8 |
320 |
|
|
1 |
Laptop |
Dell Latitude E6220 |
2012 |
i5 |
8 |
128 |
|
|
1 |
Laptop |
Dell Latitude E6320 |
2012 |
i5 |
8 |
256 |
Bildschirm klappert |
|
1 |
Laptop |
Dell Latitude E6520 |
2012 |
i5 |
8 |
320 |
|
|
|
|
|
|
|
|
|
|
|
1 |
Laptop |
MacBook Pro 13" |
2011 |
i7 |
4 |
- |
|
|
1 |
Laptop |
MacBook Pro 15" |
2012 |
i7 |
8 |
- |
Autor: Thomas Niedermeier
GCSnews des Gauss Centre for Supercomputing (GCS)
Die aktuelle Ausgabe der GCSnews des Gauss Centre for Supercomputing (GCS) finden Sie hier . Alle Ausgaben sind über die Webseite des GCS verfügbar.Das Gauss
Centre for Supercomputing(GCS) ist der Zusammenschluss der
drei nationalen Höchstleistungsrechenzentren in Deutschland (FZ Jülich,
HLRS in Stuttgart und LRZ in Garching bei München). GCS ist der
deutsche Partner in der Partnership for Advanced Computing in Europe
(PRACE).
Infobrief der Gauß-Allianz
Die Gauß-Allianz (GA) ist der Zusammenschluss von 18 Rechenzentren und Institutionen in Deutschland zur nachhaltigen und effizienten Nutzung von Supercomputing-Ressourcen der obersten Leistungsklassen. Hier finden Sie die aktuelle Ausgabe des GA-Infobriefs.Die Gauß-Allianz schreibt den Namen des großen Mathematikers mit "ß", das Gauss Centre schreibt seinen Namen in britischem Englisch mit "ss" statt "ß".
PRACE Newsletter
PRACE, the Partnership for Advanced Computing in Europe , was established in 2010 to create a persistent pan-European Research Infrastructure (RI) of world-class supercomputers. This infrastructure is currently made up of seven leading edge machines, hosted by five member countries, (France, Germany, Italy, Spain and Switzerland) and is accessible through an open peer-review process, complemented by national resources operated and accessible via High Performance Computing (HPC) centres throughout Europe. To receive PRACE' newsletter, please go to http://www.prace-ri.eu/subscribe-to-prace-gdpr-compliance/Termine, Kurse und Veranstaltungen
Firewall:
Einführungs- und Fortgeschrittenen-Kurs am LRZ
Das LRZ bietet wieder verschiedene Kurse für die virtuellen Firewalls (pfsense) an.
Einführungskurse (Grundbedienung) finden am 20.05 / 23.07 / 19.09 statt.
Erweiterte Kurse (Einrichtung VPN, NAT etc.) finden am 29.05. und 24.07 statt.
Die Kurse finden jeweils von 15:00 bis 16:30 (Ausnahme: 19.09 10:00-12:00 Uhr )
am LRZ statt. Anmeldung nur über unsere Kurs-Webseite.
Autor: Philipp Tunka
Frühjahrstreffen des Arbeitskreises "Multimedia & Grafik" des ZKI
Das Frühjahrstreffen des Arbeitskreises "Multimedia & Grafik" des ZKI e.V. findet vom 21. bis 23.05.2019 am LRZ in Garching bei München statt.- Beginn des Rahmenprogramms am Dienstag, 21.5.2019, um 17:30 Uhr mit einer Altstadtführung in München, Treffpunkt Marienplatz an der Mariensäule
- Beginn Frühjahrstreffen: Mittwoch, 22.5.2019, ab 08:30 Uhr
- Ende: Donnerstag, 23.5.2019, 15:00 Uhr
Autor: Maxime Pedrotti
PRACE Workshop: HPC code optimisation workshop
Date:
Monday, May 20 - Wednesday, May 22, 2019, 9:00-17:00
Lecturers: Dr. Fabio Baruffa (Intel), Dr.
Mathias Gerald (LRZ), Dr. Luigi Iapichino (LRZ)
Further Details and Registration: https://events.prace-ri.eu/event/872/
Registration deadline: 6 May 2019
Location: LRZ Building, University campus Garching,
near Munich, Germany
In the ever-growing complexity of computer architectures, code optimization has become the main route to keep pace with hardware advancements and effectively make use of current and upcoming High Performance Computing systems.
Have you ever asked yourself:
- Where does the performance of my application lay?
- What is the maximum speed-up achievable on the architecture I am using?
- Is my implementation matching the HPC objectives?
In this workshop, experts from LRZ and Intel will answer these questions and provide a unique opportunity to learn techniques, methods and solutions on how to improve code, how to enable the new hardware features and how to use the roofline model to visualize the potential benefits of an optimization process.
We will begin with a description of the latest micro-processor architectures and how the developers can efficiently use modern HPC hardware, in particular the vector units via SIMD programming and AVX-512 optimization and the memory hierarchy.
The attendees are then conducted along the optimization process by means of hands-on exercises and learn how to enable vectorization using simple pragmas and more effective techniques, like changing data layout and alignment.
The work is guided by the hints from the Intel® compiler reports, and using Intel® Advisor.
NEW: this year the workshop will consist of three days. We will dedicate most of the third day to the Intel Math Kernel Library (MKL), in order to show how to gain performance through the use of libraries.
We provide also an N-body code, to support the described optimization solutions with practical hands-on.
The course is a PRACE training event.
Autor: Volker Weinberg
Introduction to Intel FPGA Programming Models
Date:
Tuesday, May 21, 2019, 09:00-17:00
Lecturers: Bill Jenkins (Intel)
Further Details and Registration: https://www.lrz.de/services/compute/courses/2019-05-21_hfpg1s19/
Registration deadline: 6 May 2019
Location: LRZ Building, University campus Garching,
near Munich, Germany
FPGAs can help accelerate many of the core data center workloads that process the growing volume of data that our hyper-connected world creates. They can be reprogrammed in a fraction of a second with a datapath that exactly matches your workload’s key algorithms. This versatility results in a higher performing, more power efficient, and well utilized data center – lowering your total cost of ownership. FPGAS can be connected directly to processors, memories, networks, and numerous other interfaces. Traditionally, FPGAs require deep domain expertise to program for, but Intel is investing in significantly simplifying the development flow and enable rapid deployment across the data center.
This full day course offered by Intel in cooperation with LRZ is a high-level overview of FPGAs with the intention of level setting people on what they are, why they are so important as accelerators, what their programming models are and how easily they can be adopted into compute clusters through the use of the Acceleration Stack for Intel® Xeon® CPU with FPGAs. This course contains both lecture and lab exercises to help gain familiarity with these concepts using the tools available for FPGA developers such as Quartus, Platform Designer, High Level Synthesis, OpenCL, and DSP Builder.
At completion you will have learned:
- Why FPGA accelerators are so important in solving tomorrows problems
- Identify the various programming models for the FPGA
- Understand the components of the Acceleration Stack and where to get them and how to use them
- Explain the software development model for writing software applications using the OPAE layer to run acceleration workloads on an FPGA accelerator
- Where to get or how to create accelerator workloads for Programmable Accelerator Cards (PAC) using the Acceleration Stack for Intel® Xeon® CPU with FPGAs
NEW PRACE Course: Deep Learning and GPU programming workshop @ LRZ
Date: Monday, June 3 - Thursday, June 6, 2019, 9:00-17:00Location: LRZ
Lecturer: Dr. Momme Allalen, Dr. Juan Durillo
Barrionuevo, Dr. Yu Wang, Dr. Volker Weinberg
(LRZ)
Summary: This new 4-days PRACE
workshop offered for the first time at LRZ combines lectures about
fundamentals of Deep Learning for Multiple Data Types and Multi-GPUs
with lectures about Accelerated Computing with CUDA C/C++ and OpenACC.
Further information: https://events.prace-ri.eu/event/860/
NEW: Deep Learning and GPU programming using OpenACC @ HLRS Stuttgart
Date: Monday, July 15 -
Wednesday, July 17, 2019, 9:00-17:00
Location: HLRS,
University of Stuttgart, Nobelstr. 19, D-70569 Stuttgart, Germany
Lecturer: Yu
Wang (LRZ), Volker Weinberg (LRZ), Momme Allalen (LRZ)
Summary: The workshop combines
lectures about fundamentals of Deep Learning for Computer Vision and
Multiple Data Types with a lecture about Accelerated Computing with
OpenACC.
Further information: http://www.hlrs.de/training/2019/DL1
All lectures are interleaved with many hands-on sessions using Jupyter Notebooks. The exercises will be done on a fully configured GPU-accelerated workstation in the cloud.
All involved instructors are NVIDIA certified University Ambassadors.
Autor: Volker Weinberg
Next HPC Courses and Workshops at LRZ
Following, please, find a list of the next HPC courses at LRZ- PRACE Workshop: HPC code optimisation workshop
- Monday, May 20 - Wednesday, May 22, 2019, 9:00-17:00
- Introduction to Intel FPGA Programming Models
- Tuesday, May 21, 2019, 09:00-17:00
- PRACE Course: Deep Learning and GPU programming workshop
- Monday, June 3 - Thursday, June 6, 2019, 9:00-17:00
- Advanced C++ with Focus on Software Engineering
- Wednesday, June 12 - Friday, June 14, 2019, 9:00 - 17:00
- Deep Learning and GPU programming using OpenACC @ HLRS Stuttgart
- Monday, July 15 - Wednesday, July 17, 2019, 9:00-17:00
- Introduction to ANSYS Fluid Dynamics (CFX, Fluent) on LRZ HPC Systems
- Monday, September 2 - Friday, September 6, 2019, 09:00-17:00
- Advanced C++ with Focus on Software Engineering
- Wednesday, November 20 - Friday, November 22, 2019, 9:00 - 17:00
- C++ Language for Beginners
- Monday, November 25 - Friday, November 29, 2019, 9:00 - 17:00
- Past Courses
- Archive of previous courses
- Other Courses
- Courses at other GCS and PRACE locations
- Resources
- Lecture Notes of Courses & Workshops
Information on further HPC courses:
- by LRZ: http://www.lrz.de/services/compute/courses/
- by the Gauss Centre of Supercomputing (GCS): http://www.gauss-centre.eu/training
- by German Centres (collected by the Gauß-Allianz): https://hpc-calendar.gauss-allianz.de/
- by the Partnership for Advanced Computing in Europe (PRACE): http://www.training.prace-ri.eu/
Stellenangebote / Job Opportunities
Sie finden alle aktuellen Stellenangebote des LRZ immer auf unser Webseite www.lrz.de/wir/stellen/.
You will find all job opportunities at LRZ, some of them in English, on our web page www.lrz.de/wir/stellen/.
Impressum
Herausgeber:
Leibniz-Rechenzentrum der Bayerischen Akademie der Wissenschaften
Anschrift:
Leibniz-Rechenzentrum der Bayerischen Akademie der Wissenschaften
Boltzmannstraße 1
D-85748 Garching
Telefon: +49-89-35831-8000
Telefax: +49-89-35831-9700
E-Mail: lrzpost_AT_lrz.de
Redaktion: Dr. Ludger Palm
Sollten Sie Schwierigkeiten mit der Darstellung unseres Newsletters haben, dann schicken Sie uns bitte eine kurze Beschreibung des Problems an NewsletterRedaktion_AT_lrz.de . Danke!
Bestellen und Abbestellen des Newsletters
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