ONLINE: Optimizing OpenCL Programs for Intel FPGAs

Date: Thursday, June 25, 2020, 09:00-18:00 CEST
Location: ONLINE

Contents:

This course will be delivered as an ONLINE COURSE for remote participation because of the COVID-19 measures enforced by most European governments.

REGISTRATION is strictly NECESSARY since the details to access the online course will be provided to the registered and accepted attendees only.

FPGAs can help accelerate many of the core data center workloads that process the growing volume of data that our hyper-connected world creates. They can be reprogrammed in a fraction of a second with a datapath that exactly matches your workload’s key algorithms. This versatility results in a higher performing, more power efficient, and well utilized data center – lowering your total cost of ownership. FPGAS can be connected directly to processors, memories, networks, and numerous other interfaces. Traditionally, FPGAs require deep domain expertise to program for, but Intel is investing in significantly simplifying the development flow and enable rapid deployment across the data center.

The course covers various optimization techniques to implement high performance OpenCL™ applications on FPGAs. We'll use various debug & analysis tools available in the Intel® FPGA SDK for OpenCL™ software technology to boost performance of OpenCL kernels. The first half of the lecture focuses on the optimization of single work-item kernels & the utilization of channel constructs & OpenCL kernel pipes. The second half of the lecture focuses on the optimization of NDRange kernels & the effective utilization of FPGA memory resources. Throughout the lecture we will discuss good coding practices for FPGAs & tool features to improve OpenCL kernel performance on FPGAs.

After this lecture you will be able to:

  • Use debugging & optimization tools
  • Execute multiple OpenCL kernels in a task parallel fashion
  • Boost performance of single work-item kernels
  • Use single work-item kernels to implement parallel programming algorithms
  • Use channels or OpenCL kernel pipes to increase communication performance
  • Boost performance of NDRange kernels
  • Improve usage of memory architectures
  • Improve host-device communication efficiency
  • Use good coding practices
  • Boost data processing efficiency

The course is offered by Intel in cooperation with LRZ using the Webex Training platform.

Please use your own laptop for the hands-on sessions! Please mind that the lab access in the Webex Training platform is only supported under Windows. Participants using macOS or Linux are encouraged to download and install a Windows 10 development environment via https://developer.microsoft.com/en-us/windows/downloads/virtual-machines


OpenCL    intel

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of Khronos.
Prerequisites Basic understanding of the OpenCL programming model as offered in the course OpenCL Programming for Intel FPGAs

The content level of the course is broken down as:

Beginner's content: 0,0h 0%
Intermediate content: 4,0h 50%
Advanced content: 4,0h 50%
Community-targeted content: 0,0h 0%
Language: English
Lecturer: Marlon Price (Intel)
Registration:

Via the LRZ registration form. Please choose course HFPG3S20.

Please note: This course is offered in cooperation with Intel Corp. Germany. Some of your personal data will be transferred to Intel (first name, surname, institution, faculty, email, course). The legal basis is in accordance with Article 6(1)(b) GDPR. Please see also our data protection notice (in German: https://www.lrz.de/datenschutzerklaerung/).
Hands-on:

Will be offered via the Webex Training platform.
Contact: Dr. Volker Weinberg (LRZ)
Fee: The online course is free of charge for people from academia and industry.