PRACE Workshop: Intel Manycore Programming Workshop

Annotation

The course discusses programming models and optimisation techniqes for Intel manycore processors in order to enable programmers to achieve good performance of their applications. The course will concentrate on techniques also relevant for the latest Intel® Xeon® Scalable processor, code-named Skylake, which is going to be utilized in the upcoming SuperMUC-NG machine at LRZ. Futhermore programming and optimisation techniques for Intel Knights Landing (KNL) based systems like the KNL cluster CoolMUC3  at LRZ will be discussed.

The workshop covers a wide range of topics from the description of the hardware of the Intel processors through information about the basic programming models as well as information about vectorisation and MCDRAM usage up to tools and strategies how to analyse and improve the performance of applications.

Topics covered will include:

• Overview of the Intel Skylake and MIC architecture
• Overview of programming models
• Vectorisation and basic performance optimisation
• Code optimization process for Intel processors
• Intel profiling tools and roofline model
• KNL memory modes and cluster modes, MCDRAM
• Advanced OpenMP programming on Intel processors
• Advanced optimisation techniques

Agenda:

Monday, July 16, 2018, Seminarraum 1, H.E.008

09:00-10:00 Welcome & Introduction (Volker Weinberg, LRZ)

10:00-10:30 Overview of the Intel Skylake and MIC architecture (Momme Allalen, LRZ)

10:30-11:00 Coffee Break

11:00-11:30 Overview of programming models & Using the LRZ Linux-Cluster (Momme Allalen, LRZ)

11:30-12:00 Hands-on

12:00-13:00 Lunch break

13:00-14:00 Guided SuperMUC/CoolMUC-3 Tour (Weinberg/Allalen)

14:00-15:00 Vectorisation and basic performance optimisation (Momme Allalen, LRZ)

15:00-15:30 Coffee break

15:30-16:00 Hands-on

Tuesday, July 17, 2018, Seminarraum 1, H.E.008

09:00-10:30 KNL Memory Modes and Cluster Modes, MCDRAM (Volker Weinberg, LRZ)

10:30-11:00 Coffee Break

11:00-12:00 Hands-On

12:00-13:00 Lunch break

13:00-14:30 Code optimization process (Luigi Iapichino, LRZ)

14:30-15:00 Coffee Break

15:00-16:00 Intel profiling tools and roofline model (Luigi Iapichino, LRZ)

Wednesday, July 18, 2018, Hörsaal, H.E.009

10:00-12:00 Public Lecture: “Taming Intel Xeon Processors with OpenMP” (Michael Klemm, Intel)

                    Flyer for this part of course

12:00-13:00 Lunch break

Wednesday, July 18, 2018, Seminarraum 1, H.E.008

13:00-14:30 Advanced optimisation techniques (J. Eitzinger, RRZE)

14:30-15:00 Coffee Break

15:00-16:00 Intel Skylake programming using Intrinsics and Assembler (J. Eitzinger, RRZE)

The workshop will include both theoretical and practical hands-on sessions.

Please bring your own laptop (with an ssh client installed) for the hands-on sessions!

Figure: Participants of the Manycore Workshop 2018

The course is a PRACE Advanced Training Center event.

About the tutors

Dr. Momme Allalen received his Ph.D in theoretical Physics from the University of Osnabrück in 2006. He worked in the field of molecular magnetics through modelling techniques such as the exact numerical diagonalisation of the Heisenberg model. He joined the Leibniz Computing Centre (LRZ) in 2007 working in the High Performance Computing group and he is actually leading the LRZ CFD-Lab. His tasks include high level support, training, optimisation of scientific application codes on novel architectures, and extreme-scale computing. His research interests are various aspects of parallel computing and new programming languages and paradigms.

Dr.-Ing. Jan Eitzinger (RRZE) (formerly Treibig) holds a PhD in Computer Science from the University of Erlangen. He is now a postdoctoral researcher in the HPC Services group at Erlangen Regional Computing Center (RRZE). His current research revolves around architecture-specific and low-level optimization for current processor architectures, performance modeling on processor and system levels, and programming tools. He is the developer of LIKWID, a collection of lightweight performance tools. In his daily work he is involved in all aspects of user support in High Performance Computing: training, code parallelization, profiling and optimization, and the evaluation of novel computer architectures.

Dr. Luigi Iapichino holds a position of scientific computing expert at LRZ and he is member of the Intel Parallel Computing Center (IPCC). His main tasks are code modernization for many-core systems, and HPC support. He got in 2005 a PhD in physics from TU München, working at the Max Planck Institute for Astrophysics. Before moving to LRZ in 2014, he worked at the Universities of Würzburg and Heidelberg, involved in research projects related to computational astrophysics.

Dr.-Ing. Michael Klemm is part of the Developer Relations Division at Intel. His focus is on High Performance and Throughput Computing. He received a Doctor of Engineering degree (Dr.-Ing.) in Computer Science from the Friedrich-Alexander-University Erlangen-Nuremberg, Germany.  His areas of interest include compiler construction, design of programming languages, parallel programming, and performance analysis and tuning. Michael is Intel representative in the OpenMP Language Committee and is also the Chief Executive Officer of the OpenMP Architecture Review Board.

Dr. Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is responsible for HPC and PATC (PRACE Advanced Training Centre) courses at LRZ, new programming languages and the Intel Xeon Phi based system SuperMIC. Within PRACE-4IP he took over the leadership to create Best Practice Guides for new architectures and systems.

Fees

The event is provided free of charge for the participants.

Capacity

48 attendees