PRACE-3IP: Third Implementation Phase Project

The purpose of the PRACE Research Infrastructure is to provide a sustainable high-quality infrastructure for Europe that can meet the most demanding needs of European HPC user communities through the provision of user access to the most powerful HPC systems available worldwide at any given time. In tandem with access to Tier-0 systems, the PRACE project will foster the coordination between national HPC resources (Tier-1 systems) to best meet the needs of the European HPC user community.

PRACE-3IP is designed to continue, extend and complement the previous and on-going work in the implementation phase of the PRACE Research Infrastructure. This involves providing a long-term, high-quality infrastructure for European Tier-0 systems, managing the coordination between the shared portion of the national HPC resources (Tier-1 systems), and strengthening the established relationships with industrial users. PRACE-3IP will add a new key activity to the PRACE RI: the use of Pre-Commercial Procurement (PCP).The following four activities are central to PRACE-3IP:

• Pre-Commercial Procurement: Pilot exercise for a joint procurement and joint ownership of innovative HPC prototypes, focusing on high-energy efficiency.
• Deployment of HPC services for European industry: Proposes a broad set of services suitable for use by industry, including access to HPC resources, knowledge transfer through application support, training and expertise.
• Application scaling and support to address major socio-economic challenges: Tackles major socio-economic challenges and the use of simulation and modelling to deal with them.
• Training and outreach for growth: Establishes broad training and outreach activities specifically designed to engage more user communities, including industry, in the use of HPC systems.

The work of PRACE-3IP and its objectives are structured into eight Work Packages that address the requirements of the European HPC ecosystemRZ contributed to WP2 “Policies and Procedures”, WP6 “Operation of the Distributed Research Infrastructure”, and WP7 “Application Enabling and Support”.

Highlights

Publications

Barth M., Byckling M., Ilieva N., Saarinen S., Schliephake M., Weinberg V. (Editors), Best Practice Guide Intel Xeon Phi v1.1, http://www.prace-ri.eu/IMG/pdf/Best-Practice-Guide-Intel-Xeon-Phi.pdf, February 2014

Weinberg V., Allalen M., First Intel MIC & GPU Programming Workshop at LRZ. In: Inside, Innovatives Supercomputing in Deutschland, Vol. 12,No. 2, November 2014

Eide V., Lioen W., Szpindler M., Weinberg V., Petascaling and Optimisation for Tier-1 Architectures, May 2013, http://www.prace-ri.eu/IMG/pdf/d7.3.pdf.

Scott B. D., Weinberg V., Hoenen O., Karmakar A., Fazendeiro L., Scalability of the plasma physics code GEM, PRACE Whitepaper, Dec 2013, http://arxiv.org/abs/1312.1187

The following reports were prepared:
Final Report on Applications Enabling (http://www.prace-ri.eu/IMG/pdf/d7.1.2_3ip.pdf)
Second Annual Technology Report (http://www.prace-ri.eu/IMG/pdf/d6.3.2_3ip.pdf )
Second Annual Operations Report (http://www.prace-ri.eu/IMG/pdf/d6.1.2_3ip.pdf )

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